GOA driving circuits and display devices

A gate driver on array (GOA) driving circuit, comprising:

• N number of cascaded-connected GOA units, wherein N is a natural number not smaller than four, wherein the GOA unit at the i-th level comprises a first transistor, a second transistor;
• a third transistor, a first capacitor, and a first pull-down maintain unit, wherein 1≤i≤a and a is a natural number smaller than or equal to N/2;
• a source and a gate of the first transistor receives turn-on signals, and a drain of the first transistor respectively connects to the first pull-down maintain unit and a node at the i-th level;
• a source of the second transistor receives the turn-on signals, a gate of the second transistor receives second clock signals, and a drain of the second transistor connects to the node at the i-th level;
• a source of the third transistor receives first clock signals, a gate of the third transistor connects to the node at the i-th level, and a drain of the third transistor respectively connects to the other end of the first capacitor and a gate signal output end at the i-th level;
• one end of the first capacitor connects to the node at the i-th level, and the other end of the first capacitor connects to the first pull-down maintain unit, the first pull-down maintain unit connects to a direct-current low voltage end;
• the GOA unit at the j-th level comprises a fourth transistor, a fifth transistor, a second capacitor, and a second pull-down maintain unit, wherein a+1≤j≤N;
• a source of the fourth transistor connects to a gate signal output end in the (j−a)-th level, a gate of the fourth transistor receives the second clock signals, a drain of the fourth transistor respectively connects to second pull-down maintain unit and the node at the j-th level Q(j);
• a source of the fifth transistor receives the first clock signals, a gate of the fifth transistor connects to the node at the j-th level Q(j), and a drain of the fifth transistor respectively connects to the other end of the second capacitor and the gate signal output end at the j-th level;
• and one end of the second capacitor connects to the node in the j-th level, and the other end of the second capacitor connects to the second pull-down maintain unit, and the second pull-down maintain unit connects to a turn-off voltage;
• and
• wherein the second clock signals and the first clock signals are two different clock signals in one clock signals set;
• the clock signals set comprises M number of clock signals, wherein M is a positive integer, wherein a period of each of the clock signals is 8H, and a high level duration of each of the clock signals is 3.2H, a rising edge of the (m+1)-th clock signals is delayed by a time delay of the rising edge of the m-th clock signals, wherein m is a positive integer in a range from 1 to M, and m is not equal to three, the rising edge of the third clock signals is delayed by 1.2H of the rising edge of the second clock signals.