Inspection method, inspection system, and method of manufacturing semiconductor package using the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYounghoon Sohn, Yusin Yang
Life of this patent
Estimating the term…
Abstract
An inspection method includes generating first layout data including information on a shape of a first pattern group, generating second layout data including information on a shape of a second pattern group, obtaining a target image including images of the first and second pattern groups, and detecting a defect pattern from the target image by comparing the first and second layout data with the target image. The first pattern group, the second pattern group, and the defect pattern are provided at different heights from each other, from a top surface of a substrate.
Claims20
A method of manufacturing a semiconductor package, the method comprising:
- forming a first pattern group on a substrate;
- measuring a first image of the first pattern group to generate first layout data based on the first image;
- forming an interlayer layer on the first pattern group;
- forming a second pattern group on the interlayer layer;
- measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer;
- measuring a third image including the first image and the second image to generate third layout data based on the third image;
- and
- detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.
A method of manufacturing a semiconductor package, the method comprising:
- forming a first pattern group on a substrate;
- measuring a first image of the first pattern group to generate first layout data based on the first image, the first image obtained using a first light source;
- forming an interlayer layer on the first pattern group;
- forming a second pattern group on the interlayer layer;
- measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer, the second image obtained using the first light source;
- measuring a third image including the first image and the second image to generate third layout data based on the third image, the third image obtained using a second light source different from the first light source;
- and
- detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.
A method of manufacturing a semiconductor package, the method comprising:
- forming a first pattern group on a substrate;
- measuring a first image of the first pattern group to generate first layout data based on the first image, the first image obtained using a first light source configuring a dark-field illumination system;
- forming an interlayer layer on the first pattern group;
- forming a second pattern group on the interlayer layer;
- measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer, the second image obtained using the first light source;
- measuring a third image including the first image and the second image to generate third layout data based on the third image, the third image obtained using a second light source configuring a bright-field illumination system;
- and
- detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.
Dependencies are inferred from the claim text.