Method and apparatus for processing image enhancement algorithm

An image enhancement algorithm processing apparatus comprising:

• a hardware accelerator;
• a processor configured to:
• set a control register defining a second function while the hardware accelerator is performing a first function,
• index and store the set control register in a buffer, and
• after the hardware accelerator performs the first function, command the hardware accelerator to perform the second function defined by the set control register;
• and
• a memory configured to be shared by the processor and the hardware accelerator,
• wherein data is read from the memory and is stored in the buffer,
• wherein a first priority is assigned to the processor and a second priority is assigned to the hardware accelerator,
• wherein the processor is further configured to assign the second priority of the hardware accelerator to be higher than the first priority assigned to the processor,
• wherein, when the processor and the hardware accelerator access the buffer, the processor and the hardware accelerator access the buffer in an order according to the assigned priorities,
• wherein the hardware accelerator comprises a plurality of hardware accelerators, and
• wherein each of the plurality of hardware accelerators comprises a priority that is higher than the first priority assigned to the processor.

An image enhancement algorithm processing method performed by a processor, the image enhancement algorithm processing method comprising:

• setting a plurality of different control registers;
• indexing and storing the plurality of different control registers in a buffer;
• calling a first control register corresponding to a first index among the plurality of different control registers stored in the buffer by using the first index;
• commanding a hardware accelerator to perform a first function defined by the called first control register;
• storing data read from a memory shared by the processor and the hardware accelerator, in the buffer;
• assigning a first priority to the processor and a second priority to the hardware accelerator;
• and
• accessing the buffer in an order according to the assigned priorities, in response to the processor and the hardware accelerator accessing the buffer,
• wherein the assigning of the first and second priorities comprises assigning the second priority of the hardware accelerator to be higher than the first priority assigned to the processor,
• wherein the hardware accelerator comprises a plurality of hardware accelerators, and
• wherein each of the plurality of hardware accelerators comprises a priority that is higher than the first priority assigned to the processor.