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US 10,482,562 B2Granted
Graphics engine partitioning mechanism
AssigneeIntel Corporation
InventorsAbhishek R. Appu, Balaji Vembu, Altug Koker, Bryan R. White, David J. Cowperthwaite, Joydeep Ray, Murali Ramadoss
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Abstract
An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.
Claims19
An apparatus comprising:
- one or more processors including one or more graphics processing units (GPUs), the one or more GPUs including a plurality of graphics processing engines, the plurality of graphics processing engines including at least a first graphics processing engine and a second graphics processing engine;
- a configurable interface;
- and
- an engine synchronizer;
- wherein the one or more GPUs are to partition the plurality of graphics processing engines to facilitate independent access to each graphics processing engine within the plurality of graphics processing engines such that access to the first graphics processing engine can be provided to a client without providing the client access to the second graphics processing engine and such that operation of the first graphics processing engine does not interfere with operation of the second graphics processing engine;
- and
- wherein partitioning the plurality of graphics processing engines includes the one or more GPUs to utilize the configurable interface to implement a plurality of configurations to provide independent access to each of the plurality of graphics processing engines and includes the engine synchronizer to maintain inter-engine synchronization between the plurality of graphics processing engines in operation using message control between the plurality of graphics processing engines.
4 more elements
A graphics device comprising:
- one or more processors including one or more graphics processing units (GPUs), the one or more GPUs including a plurality of graphics processing engines, the plurality of graphics processing engines including at least a first graphics processing engine and a second graphics processing engine;
- a configurable interface;
- and
- an engine synchronizer;
- wherein the one or more GPUs are to partition the plurality of graphics processing engines for independent access to each graphics processing engine within the plurality of graphics processing engines by one or more virtual machines (VMs) such that access to the first graphics processing engine can be provided to a VM without providing the VM access to the second graphics processing engine and such that operation of the first graphics processing engine does not interfere with operation of the second graphics processing engine;
- and
- wherein partitioning the plurality of graphics processing engines includes the one or more GPUs to utilize the configurable interface to implement a plurality of configurations to provide independent access to each of the plurality of graphics processing engines and includes the engine synchronizer to maintain inter-engine synchronization between the plurality of graphics processing engines in operation using message control between the plurality of graphics processing engines.
4 more elements
A system comprising:
- one or more processors including one or more graphics processing unit (GPUs), the one or more GPUs including a plurality of graphics processing engines, the plurality of graphics processing engines including at least a first graphics processing engine and a second graphics processing engine;
- a configurable interface;
- and
- an engine synchronizer;
- wherein the one or more GPUs are to support a plurality of virtual machines (VMs) including at least a first VM and a second VM;
- wherein the one or more GPUs are to:
- partition the plurality of graphics processing engines for independent access to each graphics processing engine within the plurality of graphics processing engines by the plurality of VMs such that access to the first graphics processing engine can be provided to a VM without providing the VM access to the second graphics processing engine and such that operation of the first graphics processing engine does not interfere with operation of the second graphics processing engine, wherein partitioning the plurality of graphics processing engines includes the one or more GPUs to utilize the configurable interface to implement a plurality of configurations to provide independent access to each of the plurality of graphics processing engines and includes the engine synchronizer to maintain inter-engine synchronization between the plurality of graphics processing engines in operation using message control between the plurality of graphics processing engines.
4 more elements
Dependencies are inferred from the claim text.