Interconnection scheme for reconfigurable neuromorphic hardware

A reconfigurable neuromorphic processor logic unit, comprising:

• a plurality of corelets, each corelet to include:
• a plurality of synapse arrays, each synapse array to include:
• a plurality of synapses, each synapse to include:
• a synapse input;
• a synapse output;
• and
• a synapse memory to store a synapse destination of the corresponding synapse and a synapse weight for the corresponding synapse;
• a synapse array router, the synapse array router coupled to the synapse outputs in the synapse array;
• a neuron array, including a plurality of neurons, each of the plurality of neurons including a neuron input and a neuron output;
• wherein each synapse array router includes circuitry to:
• read at least one synapse memory;
• identify a corresponding synapse destination;
• identify a corresponding synapse weight;
• and
• transmit a packet including the synapse weight and the corresponding synapse destination to a particular neuron group router, based on a routing algorithm.