Automated resistance and capacitance extraction and netlist generation of logic cells

A system for aiding development of an integrated circuit fabrication process, the system comprising a memory and a data processor coupled to the memory, the data processor configured with:

• a source of a layout of a circuit design, the circuit design including at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor of the circuit design or a pin of the circuit design;
• a source of a description of a fabrication process under test;
• a layout identifier;
• a fabrication process simulator;
• a parasitic resistance and capacitance estimator;
• a netlist annotator;
• and
• a flow controller which is programmed to:
• operate the layout identifier to identify, from the layout, locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout;
• operate the fabrication process simulator to synthesize, by the fabrication process under test, a three-dimensional circuit representation fabricated in accordance with the layout of the circuit design, the three-dimensional circuit representation including at least the interconnects provided in the layout of the circuit design and the locations of the plurality of interconnect endpoints identified from the layout;
• operate the parasitic resistance and capacitance estimator to estimate, from three-dimensional circuit representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect;
• operate the parasitic resistance and capacitance estimator to estimate, from the three-dimensional circuit representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design;
• operate the netlist annotator to develop an annotated netlist that includes the plurality of the transistors identified from the layout and the plurality of the interconnects identified from the layout, and which further indicates the parasitic resistance and parasitic capacitance values estimated from the three-dimensional circuit representation;
• and
• write the annotated netlist into a storage device in conjunction with the parasitic resistance values and parasitic capacitance values for use by a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test.

A non-transitory computer readable medium having stored thereon a plurality of instructions which when executed by a processor aids development of an integrated circuit fabrication process when provided with a layout of a circuit design, the circuit design including at least one pin, at least one transistor and at least one conductor, at least one of the conductors being an interconnect, each of the interconnects having at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design, the plurality of instructions comprising instructions that cause the processor to:

• identify, from the layout, locations for a plurality of transistors in the layout and a plurality of interconnect endpoints in the layout;
• synthesize by simulation of a fabrication process under test, a three-dimensional circuit representation fabricated in accordance with the layout of the circuit design, the three-dimensional circuit representation including at least the interconnects provided in the layout of the circuit design and the locations of the plurality of interconnect endpoints identified from the layout;
• estimate, from the three-dimensional circuit representation, parasitic resistance values between at least one pair of the interconnect endpoints which share an interconnect;
• estimate, from the three-dimensional circuit representation, parasitic capacitance values between at least one pair of the interconnect endpoints which are pins of the circuit design;
• develop an annotated netlist that includes the plurality of the transistors identified from the layout and the plurality of the interconnects identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation;
• and
• write the annotated netlist into a storage device in conjunction with the parasitic resistance values and parasitic capacitance values for use by a circuit simulator to produce an evaluation of the implementation of the circuit design in the fabrication process under test.