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US 10,482,209 B1Granted
Field programmable operation block array
AssigneeHLS Logix LLC
InventorsJason Daniel Gorski, Darrin Michael Hanna
Life of this patent
Estimating the term…
Abstract
A field-programmable operation array includes an interconnect network and a plurality of operation blocks, including a first operation block and a second operation block, electrically connected to the interconnect network. Each operation block includes an arithmetic logic unit and a plurality of logic gates. A pass signal output by the arithmetic logic unit of the first operation is received by the arithmetic logic unit of the second operation block.
Claims9
A field programmable operation array comprising:
- an interconnect network;
- and
- a plurality of operation blocks, including a first operation block and a second operation block, electrically connected to the interconnect network,
- wherein each operation block includes an arithmetic logic unit and a plurality of logic gates, and
- wherein a pass signal output by the arithmetic logic unit of the first operation block is received by the arithmetic logic unit of the second operation block,
- wherein each arithmetic logic unit is configured to receive two multi-bit inputs via the interconnect network, and wherein the pass signal is received by the arithmetic logic unit of the second operation block independent of the interconnect network,
- wherein each arithmetic logic unit includes an AND gate, an OR gate, and an XOR gate configured to receive the two multi-bit inputs and output a multi-bit signal,
- wherein each arithmetic logic unit includes an adder block configured to receive the two multi-bit inputs and output a multi-bit signal representing a sum of or difference between the two multi-bit inputs, and
- wherein each arithmetic logic unit includes a comparison block configured to receive the two multi-bit inputs and output a comparison signal indicating that a first of the two multi-bit inputs is greater than, less than, or equal to a second of the two multi-bit inputs.
6 more elements
An operation block for a field programmable operation array, the operation block comprising:
- an arithmetic logic unit configured to output a pass signal to another operation block in the field programmable operation array;
- and
- a plurality of logic gates including a first AND gate, a second AND gate, a first XOR gate, and a first OR gate,
- wherein the arithmetic logic unit is configured to receive two multi-bit inputs via an interconnect network, and wherein the pass signal is output to another operation block independent of the interconnect network,
- wherein the arithmetic logic unit includes a third AND gate, a second OR gate, and a second XOR gate configured to receive the two multi-bit inputs and output a multi-bit signal,
- wherein the arithmetic logic unit includes an adder block configured to receive the two multi-bit inputs and output a multi-bit signal representing a sum of or difference between the two multi-bit inputs, and
- wherein the arithmetic logic unit includes a comparison block configured to receive the two multi-bit inputs and output a comparison signal indicating that a first of the two multi-bit inputs is greater than, less than, or equal to a second of the two multi-bit inputs.
4 more elements
Dependencies are inferred from the claim text.