A method for generating a circuit for a state machine, comprising:
- dividing a plurality of states into a plurality of state groups, and each state group of the plurality of state groups comprising at least one state in the plurality of states;
- defining a plurality of jumping signals, a currently asserted jumping signal in the plurality of jumping signals making the state machine jump from a current state of the currently asserted jumping signal to a target state of the currently asserted jumping signal on a next cycle;
- classifying a jumping signal of the plurality of jumping signals of each state group of the plurality of state groups into one of three categories, the three categories comprising:
- a true jumping signal when the current state and the target state of the jumping signal of the plurality of jumping signals are different, and the target state of the jumping signal of the plurality of jumping signals belongs to the each state group of the plurality of state groups;
- a holding jumping signal when the current state and the target state of the jumping signal of the plurality of jumping signals are the same and both belong to the each state group of the plurality of state groups;
- and
- a leaving jumping signal when the current state of the jumping signal of the plurality of jumping signals belongs to the each state group of the plurality of state groups, and the target state of the jumping signal of the plurality of jumping signals does not belong to the each state group of the plurality of state groups;
- feeding each state of the plurality of states with at least one true jumping signal of a plurality of the true jumping signals, and the each state of the plurality of states being a common target state of the at least one true jumping signal of the plurality of the true jumping signals;
- feeding an initial state in the plurality of states with a synchronous initialization input signal SINI for the state machine;
- remembering each state group of the plurality of state groups by one corresponding memory group of a plurality of memory groups;
- attaching each memory group of the plurality of memory groups with one corresponding clock gating device of a plurality of clock gating devices;
- generating a clock pulse for a memory group of the plurality of memory groups on the next cycle when one of two first conditions is satisfied, the two first conditions comprising:
- the synchronous initialization input signal SINI for the state machine is asserted on a current cycle;
- or
- one state group of the plurality of state groups will make a state change on the next cycle, and the one state group of the plurality of state groups is remembered by the memory group of the plurality of memory groups;
- and
- generating a plurality of state outputs from the plurality of memory groups.