Verification support apparatus and design verification support method

A design verification support method performed by a computer coupled to a memory that stores circuit information including information on a connection destination of a component circuit included in a semiconductor having a scan chain, and a propagation delay occurring by the component circuit;

• and test pattern information indicating a test value to be input from a scan-in terminal of the scan chain at each cycle of a first clock signal output by a clock source, the design verification support method comprising:
• acquiring the circuit information and the test pattern information from the memory;
• calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information;
• selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle;
• and
• calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a first delay time calculated for the first memory circuit among delay times calculated for the plurality of memory circuits, respectively.

A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process for design verification support, the computer coupled to a memory that stores circuit information including information on a connection destination of a component circuit included in a semiconductor having a scan chain, and a propagation delay occurring by the component circuit;

• and test pattern information indicating a test value to be input from a scan-in terminal of the scan chain at each cycle of a first clock signal output by a clock source, the process comprising:
• acquiring the circuit information and the test pattern information from the memory;
• calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information;
• selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle;
• and
• calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a first delay time calculated for the first memory circuit among delay times calculated for the plurality of memory circuits, respectively.