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AssigneeCadence Design Systems, Inc.
InventorsBreno Rodrigues Guimarães, Caio Araujo Teixeira Campos, Björn Håkan Hjort
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The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, at least one electronic design file and a set of inputs from a user, wherein the at least one electronic design file and set of inputs are associated with an electronic design. Embodiments may further include performing formal verification on at least a portion of the electronic design and determining, using a model checker, one or more conflicts associated with a variable during the formal verification. Embodiments may also include translating the one or more conflicts into one or more corresponding signal names and displaying, at a graphical user interface, the corresponding signal names.
A computer-implemented method for electronic design verification comprising:
A non-transitory computer-readable storage medium for electronic design verification, the computer-readable storage medium having stored thereon instructions that when executed by a machine result in one or more operations, the operations comprising:
A system for electronic design verification comprising:
Dependencies are inferred from the claim text.