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US 10,482,205 B2Granted
Logic analyzer for integrated circuits
AssigneeXilinx, Inc.
InventorsAkhilesh Mahajan, Bokka Abhiram Sai Krishna, Keshava Gopal Goud Cheruku
Life of this patent
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Abstract
Monitoring signals in an integrated circuit can include monitoring a probed signal of an integrated circuit using a logic analyzer circuit implemented within the integrated circuit, detecting state changes in the probed signal using the logic analyzer circuit, and generating, within the logic analyzer circuit, a file specifying time stamped state changes of the probed signal.
Claims18
A method for monitoring signals in an integrated circuit, comprising:
- monitoring a probed signal within the integrated circuit using a logic analyzer circuit implemented within the integrated circuit;
- detecting state changes in the probed signal using a trace circuitry in the logic analyzer circuit, wherein the trace circuitry is configured to receive the signal and determine whether a current state of the signal is different from a prior state of the signal;
- generating, by a file generation circuit in the logic analyzer circuit coupled to the trace circuitry, ASCII encoded data specifying time stamped state changes of the probed signal, wherein the file generation circuit is configured to generate a file specifying the ASCII encoded data;
- and
- providing the file, using an interface of the logic analyzer circuit coupled to the file generation circuit, to another circuit or system.
2 more elements
An integrated circuit, comprising:
- monitored circuitry configured to generate a signal;
- and
- a logic analyzer circuit configured to monitor the signal to detect state changes in the signal and generate ASCII encoded data specifying time stamped state changes of the signal, wherein the logic analyzer circuit comprises:
- a trace circuitry configured to receive the signal and determine whether a current state of the signal is different from a prior state of the signal;
- a file generation circuit coupled to the trace circuitry, wherein the file generation circuit is configured to generate a file specifying the ASCII encoded data;
- and
- an interface coupled to the file generation circuit.
4 more elements
Dependencies are inferred from the claim text.