Method for simulating execution of an application on a multi-core processor

A computer-implemented method for simulating execution of an application on a many-core target machine, the method comprising:

• acquiring, by a processor from a host processor of the computer communicatively coupled to the processor, a base clock per instruction (CPI) of a target machine being simulated, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, the processor including a plurality of processing cores communicatively coupled one to another via respective routers;
• translating, by the host processor, the application of the target machine to a compact executable trace to be executed by the processor;
• providing, by the host processor, the compact executable trace to the processor and executing the compact executable trace on the processor;
• determining, by the processor, whether to adjust a simulation speed based on receiving a control signal from any of the routers;
• adjusting dynamically, by the processor, an update rate of a global target clock counter (GTCC) that defines the simulation speed of the processor, the update rate being based on the CPI of the target machine;
• acquiring one or more cache miss data frames and cache miss code frames from an off-chip memory controller communicatively coupled to the host processor and an off-chip memory module;
• writing one or more replacement data frames and replacement code frames back to the off-chip memory from the off-chip memory module;
• and
• providing, by the processor, simulation results to the host processor.