US 10,482,199 B2 · Thermal resistance analysis model and semiconductor integrated circuit

Abstract

A thermal resistance analysis model of a semiconductor integrated circuit comprising a die and a semiconductor chip disposed on the die, the die constituting a bottom inner node BI, the semiconductor chip including a local heat-generating portion constituting a junction node JN, the semiconductor chip constituting an additional plate node PN, a first thermal resistance θJP between the junction node JN and the additional plate node PN; and a second thermal resistance θPBI between the additional plate node PN and the bottom inner node BI, wherein the semiconductor integrated circuit is expressed by a multi-thermal resistance network. Disclosed herein are a thermal resistance analysis model with satisfactory precision as a thermal resistance analysis model of locally heat-generating semiconductor integrated circuits; and a semiconductor integrated circuit to which such a thermal resistance analysis model is applied.

Claims20

Dependent claims

A thermal resistance analysis model of a semiconductor integrated circuit comprising a die on which a semiconductor chip is disposed, the thermal resistance analysis model comprising:

a bottom inner node at the die;
a local heat-generating portion constituting a junction node and an additional plate node at the semiconductor chip;
a first thermal resistance between the junction node and the additional plate node;
and
a second thermal resistance between the additional plate node and the bottom inner node, wherein
the semiconductor integrated circuit is modeled and analyzed using a multi-thermal resistance network.

3 more elements

Dependencies are inferred from the claim text.

Thermal resistance analysis model and semiconductor integrated circuit

Life of this patent

Thermal resistance analysis model and semiconductor integrated circuit

Life of this patent

Abstract

Claims20