Programmable protocol independent bar memory for SSD controller

A method, comprising:

• defining, with a programmable bit controller, read-write properties to locations in a base address register (BAR) memory;
• receiving, with a read-write switch, a memory access request;
• identifying, with the read-write switch, whether the memory access request is a read access or a write access;
• controlling, with the read-write switch, routing of the memory access request for further processing based on the identifying operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory;
• receiving, with an access controller, the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access;
• determining, with the access controller, a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access;
• bypass the write access when the read-write property is determined to be the first read-write property;
• and
• processing, with the access controller, the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties.

A memory device, comprising:

• a programmable bit controller configured to define read-write properties to locations in a base address register (BAR) memory;
• a read-write switch configured to:
• receive a memory access request;
• identify whether the memory access request is a read access or a write access;
• and
• control routing of the memory access request for further processing based on the identify operation, wherein, when the memory access request is identified as a read access, the memory access request is routed directly to the BAR memory;
• and
• an access controller configured to:
• receive the memory access request from the read-write switch when the memory access request is identified as a write access but not when the memory access request is identified as a read access;
• determine a read-write property, among a plurality of read-write properties including a first read-write property, associated with the write access;
• bypass the write access when the read-write property is determined to be the first read-write property;
• and
• process the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request, when the read-write property is determined to be any other of the plurality of read-write properties.