Cache optimization for graphics systems
AssigneeIntel Corporation
InventorsAltug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu
Life of this patent
Estimating the term…
Abstract
A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.
Claims18
An apparatus comprising:
- one or more processors including a graphics processor, the one or more processors to:
- determine a type of each of one or more caches associated with the one or more processors;
- introduce cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits are to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches;
- upon detecting an invalidation for the one or more caches, implement and increment the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss;
- and
- facilitate replacement or re-allocation of locations of old cache coloring bits.
A method comprising:
- detecting a type of each of one or more caches associated with one or more processors including a graphics processor;
- introducing cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits are to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches;
- upon detecting an invalidation for the one or more caches, implementing and incrementing the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss;
- and
- facilitating replacement or re-allocation of locations of old cache coloring bits.
At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
- detecting one or more caches associated with one or more processors including a graphics processor;
- introducing cache coloring bits to color contents of each cache of the one or more caches associated with the one or more processors, wherein the cache coloring bits to represent a signal identifying the one or more caches as being available for use, while avoiding explicit invalidations and flushes of the one or more caches;
- upon detecting an invalidation for the one or more caches, implementing and incrementing the cache coloring bits, wherein old cache coloring bits are deemed to be invalid or a miss;
- and
- facilitating replacement or re-allocation of locations of old cache coloring bits.
Dependencies are inferred from the claim text.