Cache management method and apparatus

A buffer management apparatus, wherein the apparatus is applied to a shared buffer management system and comprises:

• a memory;
• and
• a processor, coupled to the memory,
• the processor includes a determining module, a buffer unit single allocation module and a buffer unit pairing allocation module, wherein
• the shared buffer management system has N buffer units with continuous addresses, the shared buffer management system maintains a buffer unit pair first state table and a buffer unit pair second state table, and the shared buffer management system divides the N continuous buffer units into pairs in order, wherein the buffer unit pair first state table is used to indicate whether only one buffer unit in each pair of buffer units is idle, and the buffer unit pair second state table is used to indicate whether two buffer units in each pair of buffer units are both idle;
• the determining module is configured to:
• after receiving a to-be-processed command, determine a quantity of buffer units needed by the to-be-processed command;
• and if the quantity of buffer units needed by the to-be-processed command is one, instruct the buffer unit single allocation module to perform buffer allocation, and if the quantity of buffer units needed by the to-be-processed command is two, instruct the buffer unit pairing allocation module to perform buffer allocation;
• the buffer unit single allocation module is configured to:
• search for, based on the buffer unit pair first state table, a pair of buffer units in which only one buffer unit is idle, and allocate the idle buffer unit in the pair of buffer units to the to-be-processed command;
• and
• the buffer unit pairing allocation module is configured to:
• search for and allocate, based on the buffer unit pair second state table in a clock cycle, a pair of buffer units in which two buffer units are both idle to the to-be-processed command.

A shared buffer management system, wherein the shared buffer management system comprises:

• a buffer management apparatus and N buffer units with continuous addresses, wherein the shared buffer management system further maintains a buffer unit pair first state table and a buffer unit pair second state table, and the shared buffer management system divides the N continuous buffer units into pairs in order, wherein the buffer unit pair first state table is used to indicate whether only one buffer unit in each pair of buffer units is idle, and the buffer unit pair second state table is used to indicate whether two buffer units in each pair of buffer units are both idle;
• the buffer management apparatus comprises:
• a memory;
• and
• a processor, coupled to the memory,
• the processor includes a determining module, a buffer unit single allocation module and a buffer unit pairing allocation module, wherein:
• the determining module is configured to:
• after receiving a to-be-processed command, determine a quantity of buffer units needed by the to-be-processed command;
• and if the quantity of buffer units needed by the to-be-processed command is one, instruct the buffer unit single allocation module to perform buffer allocation, and if the quantity of buffer units needed by the to-be-processed command is two, instruct the buffer unit pairing allocation module to perform buffer allocation;
• the buffer unit single allocation module is configured to:
• search for, based on the buffer unit pair first state table, a pair of buffer units in which only one buffer unit is idle, and allocate the idle buffer unit in the pair of buffer units to the to-be-processed command;
• and
• the buffer unit pairing allocation module is configured to:
• search for and allocate, based on the buffer unit pair second state table in a clock cycle, a pair of buffer units in which two buffer units are both idle to the to-be-processed command.