Providing private cache allocation for power-collapsed processor cores in processor-based systems

A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to:

• determine that a first processor core of a first processor core power domain of a plurality of processor core power domains has entered a power-collapsed state;
• and
• responsive to the first processor core entering the power-collapsed state:
• maintain power to a private cache of a private cache power domain of a plurality of private cache power domains corresponding to the first processor core power domain of the plurality of processor core power domains, wherein each private cache power domain of the plurality of private cache power domains is configured to be power-controlled independently of the corresponding processor core power domain;
• and
• enable allocation and snooping of the private cache by a second processor core of a second processor core power domain of the plurality of processor core power domains while the first processor core remains in the power-collapsed state, further responsive to determining that a configuration bit indicating whether to enable allocation and snooping of the private cache is set.

A processor-based system for providing private cache allocation, comprising:

• a plurality of processor core power domains, each comprising a processor core;
• a plurality of private cache power domains, each corresponding to a processor core power domain of the plurality of processor core power domains and comprising a private cache;
• and
• a shared cache power domain comprising a plurality of snoop controllers, each corresponding to a private cache power domain of the plurality of private cache power domains;
• wherein:
• each private cache power domain of the plurality of private cache power domains is configured to be power-controlled independently of the corresponding processor core power domain;
• and
• each snoop controller of the plurality of snoop controllers is configured to:
• determine that a first processor core of a processor core power domain associated with the snoop controller has entered a power-collapsed state;
• and
• responsive to the first processor core entering the power-collapsed state:
• maintain power to the private cache associated with the snoop controller;
• and
• enable allocation and snooping of the private cache of the private cache power domain associated with the snoop controller by a second processor core of a second processor core power domain of the plurality of processor core power domains while the first processor core remains in the power-collapsed state.

A processor-based system for providing private cache allocation, comprising:

• a means for determining that a first processor core of a first processor core power domain of a plurality of processor core power domains corresponding to a plurality of private cache power domains has entered a power-collapsed state, wherein each private cache power domain of the plurality of private cache power domains is configured to be power-controlled independently of the corresponding processor core power domain;
• a means for maintaining power to a private cache of a private cache power domain of the plurality of private cache power domains corresponding to the first processor core power domain, responsive to the first processor core entering the power-collapsed state;
• and
• a means for enabling allocation and snooping of the private cache by a second processor core of a second processor core power domain of the plurality of processor core power domains while the first processor core remains in the power-collapsed state, responsive to the first processor core entering the power-collapsed state, and further responsive to determining that a configuration bit indicating whether to enable allocation and snooping of the private cache is set.