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US 10,481,992 B1Granted
Optimization of flash storage
AssigneeEMC IP Holding Company LLC
InventorsAnthony Ginty, Cline W. Frasier, Conor Ryan, Joseph Sullivan
Life of this patent
Estimating the term…
Abstract
A method, system, and computer program product for increasing the life of a NAND flash, the method comprising selecting a set of internal control parameters for the NAND flash and optimizing the set of internal control parameters with a genetic algorithm to find an improved set of control parameters.
Claims19
A computer implemented method for increasing the life of a NAND flash, the method comprising:
- selecting a set of internal control parameters for the NAND flash;
- mapping the set of internal control parameters to a bit stream;
- and
- optimizing the set of internal control parameters with a genetic algorithm to find an improved set of control parameters, wherein the optimizing affects the threshold voltage distribution of at least one memory cell in the NAND flash, wherein the improved set of internal control parameters are run iteratively through a software model and the genetic algorithm until a stopping criteria is met, wherein the software model evaluates how the improved set of control parameters predict a number of errors in the memory cells of the NAND flash.
1 more element
A computer program product comprising:
- a non-transitory computer readable medium encoded with computer executable program code, the code:
- selecting a set of internal control parameters for a NAND flash;
- mapping the set of internal control parameters to a bit stream;
- and
- optimizing the set of internal control parameters with a genetic algorithm to find an improved set of control parameters, wherein the optimizing affects the threshold voltage distribution of at least one memory cell in the NAND flash, wherein the improved set of internal control parameters are run iteratively through a software model and the genetic algorithm until a stopping criteria is met, wherein the software model evaluates how the improved set of control parameters predict a number of errors in the memory cells of the NAND flash.
2 more elements
An apparatus for optimization of a NAND flash, the apparatus comprising:
- computer-executable program code stored in memory of the device, wherein the computer-executable program code is configured for execution on one or more processors of the following:
- selecting a set of internal control parameters for the NAND flash;
- mapping the set of internal control parameters to a bit stream;
- and
- optimizing the set of internal control parameters with a genetic algorithm to find an improved set of control parameters, wherein the optimizing affects the threshold voltage distribution of at least one memory cell in the NAND flash, wherein the improved set of internal control parameters are run iteratively through a software model and the genetic algorithm until a stopping criteria is met, wherein the software model evaluates how the improved set of control parameters predict a number of errors in the memory cells of the NAND flash.
2 more elements
Dependencies are inferred from the claim text.