Efficient testing of direct memory address translation

A computer-implemented method of testing a link processing unit on an integrated circuit, the method comprising:

• loading a first translation table with a plurality of translation entries, wherein each of the plurality of translation entries contains translation information to translate direct memory access (DMA) addresses for one of a plurality of agents connected to the integrated circuit, wherein the plurality of agents comprise a central processing unit and at least one graphics processing unit;
• testing all the translation entries in the translation table by randomly selecting an entry of the table with translation information to run multiple consecutive tests of address translation;
• providing a random signal on an input of a multiplexer;
• selecting the random signal using a select input to the multiplexer;
• and
• providing the random signal from the multiplexer to the translation table to randomly select an entry of a translation control entry table during the test mode.