Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers

An apparatus for correcting bit defects, the apparatus comprising:

• a processor;
• a memory array comprising a plurality of codewords, wherein each codeword comprises a respective plurality of redundant bits, and wherein the processor is configured to:
• determine a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for bits of the memory array, wherein the distribution of bit-cell resistances comprises a distribution of acceptable high resistance bits and a distribution of acceptable low resistance bits, wherein the margin area is between the distribution of acceptable high resistance bits and acceptable low resistance bits, wherein the bit-cell resistances of memory bit-cells associated with the margin area are not distinguished by a sense amplifier as either high or low;
• and force the bit-cell resistances of memory bit-cells associated with the margin area to short circuits in order to widen a window between the distribution of acceptable high resistance bits and acceptable low resistance bits.