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US 10,481,958 B2Granted
Speculative execution tag for asynchronous DRAM refresh
AssigneeIntel IP Corporation
InventorsThomas Willhalm, Karthik Kumar
Life of this patent
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Abstract
An embodiment of a semiconductor package apparatus may include technology to track a modification to a processor cache line, and set an indicator to indicate if the modification relates to a transaction. Other embodiments are disclosed and claimed.
Claims16
An electronic processing system, comprising:
- a processor;
- persistent memory communicatively coupled to the processor;
- and
- logic communicatively coupled to the processor to:
- track a modification to a cache line of the processor;
- set an indicator to indicate if the modification relates to a transaction, and set the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
- detect a power transition;
- determine if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition;
- and
- flush the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.
7 more elements
A semiconductor package apparatus, comprising:
- one or more substrates;
- and
- logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
- track a modification to a processor cache line;
- set an indicator to indicate if the modification relates to a transaction, and set the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
- detect a power transition;
- determine if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition;
- and
- flush the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.
6 more elements
A method of tracking a cache line modification, comprising:
- tracking a modification to a processor cache line;
- setting an indicator to indicate if the modification relates to a transaction, and setting the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
- detecting a power transition;
- determining if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition;
- and
- flushing the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.
3 more elements
At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
- track a modification to a processor cache line;
- and
- set an indicator to indicate if the modification relates to a transaction, and set the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
- detect a power transition;
- determine if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition;
- and
- flush the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.
4 more elements
Dependencies are inferred from the claim text.