Multi-queue device assignment for application groups

A system of device assignment, the system comprising:

• a physical memory;
• one or more processors, in communication with the physical memory;
• a hardware device;
• a first application associated with a first memory, the first memory being a portion of the physical memory and having a first address, executing on the one or more processors;
• a second application associated with a second memory, the second memory being a portion of the physical memory different from the first memory and having a second address, executing on the one or more processors;
• an input-output memory management unit;
• and
• a supervisor, executing on the one or more processors, to:
• receive an assignment request, wherein the assignment request is a request to assign the hardware device to a plurality of applications including at least the first application and the second application;
• select a first bus address offset and a second bus address offset, wherein the second bus address offset is different from the first bus address offset;
• send, to the first application, the first bus address offset;
• send, to the second application, the second bus address offset;
• and
• update the input-output memory management unit, including:
• updating a mapping to the first address to include the first bus address offset,
• updating a mapping to the second address to include the second bus address offset;
• and
• assign the hardware device to the first application and the second application,
• wherein the hardware device is separate and distinct from the one or more processors.

A computer-readable non-transitory storage medium comprising executable instructions that, when executed on one or more processors, cause a supervisor to:

• receive an assignment request, wherein the assignment request is a request to assign a hardware device to a plurality of applications including at least:
• a first application associated with a first memory, the first memory being a portion of a physical memory and having a first address, and
• a second application associated with a second memory, the second memory being a portion of the physical memory different from the first memory and having a second address;
• select a first bus address offset and a second bus address offset, wherein the second bus address offset is different from the first bus address offset;
• send, to the first application, the first bus address offset;
• send, to the second application, the second bus address offset;
• update an input-output memory management unit, including:
• updating a mapping to the first address to include the first bus address offset, and
• updating a mapping to the second address to include the second bus address offset;
• and
• assign the hardware device to the first application and the second application,
• wherein the hardware device is separate and distinct from the one or more processors.