Split store data queue design for an out-of-order processor

A system for wide vector execution for an out-of-order processor, the system comprising:

• a memory having computer readable instructions;
• and
• the out-of-order processor for executing the computer readable instructions, the computer readable instructions controlling the out-of-order processor to perform operations comprising:
• detecting, by the OoO processor, a mode of the OoO processor;
• partitioning, by the OoO processor, a first store data queue (SDQ) and a second SDQ based at least in part on the mode of the OoO processor;
• receiving, by the OoO processor, a vector operand;
• and
• storing, by the OoO processor, the vector operand in at least one of the first SDQ and the second SDQ based at least in part on the mode of the OoO processor,
• wherein, responsive to the mode of the OoO processor being detected to be a single thread mode, the first SDQ is partitioned to store first entries and the second SDQ is partitioned to store copies of the first entries.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an out-of-order processor to cause the out-of-order processor to perform operations comprising:

• detecting, by the OoO processor, a mode of the OoO processor;
• partitioning, by the OoO processor, a first store data queue (SDQ) and a second SDQ based at least in part on the mode of the OoO processor;
• receiving, by the OoO processor, a vector operand;
• and
• storing, by the OoO processor, the vector operand in at least one of the first SDQ and the second SDQ based at least in part on the mode of the OoO processor,
• wherein, responsive to the mode of the OoO processor being detected to be a single thread mode, the first SDQ is partitioned to store first entries and the second SDQ is partitioned to store copies of the first entries.