Circuit to perform dual input value absolute value and sum operation

A method for performing a sum of absolute difference computation by an execution unit circuit comprising a pair of arithmetic logic units (ALUs), wherein the method comprises:

• receiving, by a first ALU of the pair of ALUs, a first input value X and a second input value Y;
• computing, by the first ALU of the pair of ALUs, a difference value Q between the first input value X and the second input value Y;
• receiving, by a second ALU of the pair of ALUs, a third input value Z and the difference value Q output by the first ALU;
• computing a result of the sum of absolute difference computation including:
• adding, by the second ALU of the pair of ALUs, a sum of the third input value Z to the difference value Q whenever Q is positive, or
• subtracting, by the second ALU of the pair of ALUs, the difference value Q from the third input value Z whenever Q is negative;
• and
• outputting the computed result of the sum of absolute difference computation.

An image processor comprising a plurality of execution unit circuits, wherein each execution unit circuit comprises:

• a first input to receive a first input value X;
• a second input to receive a second input value Y;
• a third input to receive a third input value Z;
• and
• means for computing a sum of absolute difference computation from the first input value X, the second input value Y, and the third input value Z using at most two arithmetic logic unit operations.