Multi-path fused multiply-add with power control

A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including:

• pipelined multiplication circuitry that includes multiple pipeline stages and is configured to generate fused multiply-addition results;
• classification circuitry configured to classify fused multiply-addition operation based on a difference between an exponent of an addend and a sum of exponents of multiplicands;
• wherein the multiplication circuitry includes multiple paths and is configured to select paths for performing operations based on the classification, wherein the paths include:
• near-path circuitry configured to perform operations where the difference is in a first range of values between a first threshold value and a second threshold value;
• first far-path circuitry configured to perform operations where the difference is in a second range of values that does not overlap with the first range of values;
• second far-path circuitry configured to perform operations where the difference is in a third range of values that does not overlap with the first or second ranges of values;
• and
• third far-path circuitry configured to perform operations where the difference is in a fourth range of values that does not overlap with the first, second, or third ranges of values
• wherein the circuit is configured to, in response to assigning a fused multiply-addition operation to the first far-path circuitry using the classification circuitry, operate at least a portion of the near-path circuitry and at least a portion of the first second far-path circuitry in a low-power state.

A method, comprising:

• classifying, by classification circuitry, ones of a plurality of fused multiply-addition operations based on a difference between an exponent of an addend and a sum of exponents of multiplicands;
• selecting, by control circuitry, ones of multiple paths to perform ones of the plurality of fused multiply-addition operations, including:
• selecting near-path circuitry in response to the difference being in a first range of values between a first threshold value and a second threshold value;
• selecting first far-path circuitry in response to the difference being in a second range of values that does not overlap with the first range of values;
• selecting second far-path circuitry in response to the difference being in a third range of values that does not overlap with the first or second ranges of values;
• and
• selecting third far-path circuitry in response to the difference being in a fourth range of values that does not overlap with the first, second, or third ranges of values;
• and
• in response to selecting the first far-path circuitry for an operation, operating at least a portion of the near-path circuitry and at least a portion of the first second far-path circuitry in a low-power state.