Data input/output unit, electronic apparatus, and control methods thereof

An electronic apparatus, comprising:

• a data input/output unit configured to receive and output data in sequence based on a first schedule;
• and
• a processor configured to process data based on a second schedule in which cycles of a kernel of the first schedule are reduced,
• wherein the data input/output unit comprises:
• a first-input-first-output (FIFO) memory connected to an external unit and the processor;
• and
• a reordering buffer connected to one side of the FIFO memory, and stores data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence based on the first schedule, and outputs data stored in one of the plurality of buffer regions based on a control signal provided from the processor, corresponding to a second schedule in which cycles of a kernel of the first schedule are reduced, and
• wherein the control signal indicates a buffer region in which data to be output is stored from among the plurality of buffer regions.

A method of controlling a data input/output unit, wherein the data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule, wherein the data input/output unit comprises a first-input-first-output (FIFO) memory connected to an external unit and the processor, and a reordering buffer connected to one side of the FIFO memory, the method comprising:

• storing data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions of the reordering buffer in sequence based on the first schedule;
• and
• outputting data stored in one of the plurality of buffer regions based on a control signal provided from the processor, corresponding to a second schedule in which cycles of a kernel of the first schedule are reduced,
• wherein the control signal indicates a buffer region in which data to be output is stored from among the plurality of buffer regions.