US 10,481,819 B2 · Memory devices with multiple sets of latencies and methods for operating the same

Abstract

Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Claims22

Dependent claims

A method of operating a memory device, comprising:

enabling one or more memory operation features from a set of memory operation features;
applying, from a plurality of sets of latency values, a set of latency values based at least in part on a number of enabled memory operation features;
and
executing a read command or a write command for one or more cells of the memory device based at least in part on the enabled memory operation features and the set of latency values,
wherein the one or more memory operation features comprises three features,
wherein the plurality of sets of latency values comprises three sets of latency values, and
wherein the method comprises applying a first one of the three sets of latency values when none of the three features is enabled, applying a second one of the three sets of latency values when exactly one of the three features is enabled, and applying a third one of the three sets of latency values when exactly two of the three features is enabled.

4 more elements

A memory device, comprising:

a memory array;
and
control circuitry configured to:
enable one or more memory operation features from a set of memory operation features;
and
apply, from a plurality of sets of latency values, a set of latency values based at least in part on a number of enabled memory operation features,
wherein the one or more selectable features comprises three selectable features,
wherein the plurality of sets of latency values comprises three sets of latency values, and
wherein the control circuitry is configured to apply a first one of the three sets of latency values when none of the three memory operation features is enabled, to apply a second one of the three sets of latency values when exactly one of the three memory operation features is enabled, and to apply a third one of the three sets of latency values when exactly two of the three sets of latency values are enabled.

6 more elements

Dependencies are inferred from the claim text.

Memory devices with multiple sets of latencies and methods for operating the same

Life of this patent

Memory devices with multiple sets of latencies and methods for operating the same

Life of this patent

Abstract

Claims22