Read disturb compensation using weighted programming patterns

A data storage device comprising:

• a solid-state non-volatile memory including a plurality of memory cells;
• and
• a controller configured to improve data retention of at least a portion of the solid-state non-volatile memory at least in part by:
• reading data stored in the solid-state non-volatile memory according to a randomized programming pattern;
• reencoding the data using a programming pattern that favors a first programming state over a second programming state;
• and
• reprogramming the encoded data to the solid-state non-volatile memory.

A data storage device comprising:

• a solid-state non-volatile memory including a plurality of memory cells;
• means for encoding data using a weighted programming pattern that favors a first programming state of a second programming state, the first programming state being associated with a higher voltage level than the second programming state;
• and
• controller circuitry configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by:
• receiving or accessing data to be written to the solid-state non-volatile memory;
• encoding the data according to the weighted programming pattern using the means for encoding data;
• and
• writing the encoded data to the solid-state non-volatile memory.

A method of programming data, the method comprising:

• receiving or accessing data to be written to a solid-state non-volatile memory;
• determining that a read disturb compensation programming mode associated with the solid-state non-volatile memory is set;
• and
• in response to said determination:
• encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher programming voltage level than the second programming state;
• and
• writing the encoded data to the solid-state non-volatile memory.

A data storage device comprising:

• a solid-state non-volatile memory including a plurality of memory cells;
• and
• a controller configured to reduce bit error rate for at least a portion of the solid-state non-volatile memory at least in part by:
• accessing data to be written to the solid-state non-volatile memory;
• determining that a weighted programming mode is set;
• and
• in response to said determining that the weighted programming mode is set:
• encoding the data using a programming pattern that favors a first programming state over a second programming state;
• and
• writing the encoded data to the solid-state non-volatile memory.