Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address

A processing system, comprising:

• a processor core configured to provide a write access request, wherein the write access request has a corresponding target address and write data, and wherein the target address corresponding to the write access address has lesser significant bits and greater significant bits, in which the lesser and greater significant bits do not overlap;
• an arithmetic unit;
• and
• a hardware interface component coupled between the processor core and the arithmetic unit and having a lookup table, the hardware interface component configured to:
• receive the write access request from the processor core;
• use the lookup table of the hardware interface component to determine whether the target address corresponding to the write access request is within any one of a plurality of memory-mapped address ranges, wherein the plurality of memory-mapped address ranges are non-overlapping and wherein a different arithmetic operation is mapped to each of the plurality of memory-mapped address ranges;
• when the target address corresponding to the write access request is determined to be within a first memory-mapped address range of the plurality of memory-mapped address ranges:
• use the lesser significant bits of the target address corresponding to the write access request to identify a first input register, wherein the first memory-mapped address range includes the first input register and a result register,
• load the write data into the first input register, wherein the write data is characterized as operand data,
• identify, using the greater significant bits of the target address corresponding to the write access request, a first arithmetic operation to be performed by the arithmetic unit, wherein the first arithmetic operation is mapped to the first memory-mapped address range, and
• wherein the arithmetic unit is configured to perform the first arithmetic operation using the operand data in the first input register and loading a result of the first arithmetic operation into the result register.