Power saving for a computer system and computer based on differences between chip regions in processing and communication times

A computer system, comprising a plurality of computers,

• each of the plurality of computers including at least one processor chip each including a plurality of processor cores,
• the at least one processor chip constructing a plurality of regions each constructed by at least one processor core,
• each of the plurality of processor cores being configured to carry out calculation processing for executing a predetermined program and inter-core communication processing, which is communication between the plurality of processor cores,
• the computer system comprising:
• a regulation module configured to control a voltage and a frequency that are supplied to each of the plurality of regions;
• and
• a determination module configured to determine a power mode, which is a combination of the voltage and the frequency that are supplied to each of the plurality of regions, to output an instruction to the regulation module,
• the determination module being configured to determine the power mode of each of the plurality of regions based on a calculation amount of the calculation processing and a communication data amount of the inter-core communication processing in the at least one processor core included in the each of the plurality of regions,
• wherein the plurality of processor cores included in the at least one processor chip are coupled to one another via an intra-chip network,
• wherein a plurality of processor chips are coupled to one another via an inter-chip network,
• wherein each of the plurality of regions is defined based on an attribute of inter-core communication of the plurality of processor cores,
• wherein the inter-core communication includes intra-chip communication, which is communication among a plurality of processor cores included in a processor chip, and inter-chip communication, which is communication among a plurality of processor cores included in different processor chips,
• wherein the plurality of regions include a first region for carrying out only the intra-chip communication and a second region for carrying out the intra-chip communication and the inter-chip communication, and
• the determination module is configured to determine the power mode of each of the first region and the second region so that a difference between a sum of a processing period of the calculation processing with a communication period of the inter-core communication processing of the at least one processor core included in the first region and a sum of a processing period of the calculation processing with a communication period of the inter-core communication processing of the at least one processor core included in the second region decreases.