System on chip controlling memory power using handshake process and operating method thereof

A system on chip (SoC), comprising:

• a memory controller configured to control a memory;
• and
• a power manager configured to manage a supply power level of the memory,
• wherein the memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory,
• the power manager is configured to adjust the supply power level of the memory according to the memory access level,
• wherein the memory controller comprises a transition unit configured to inactivate a clock that is input to the memory controller, and
• the transition unit inactivates the clock occurring during a power transition interval in which the supply power level of the memory is changed.

A method of operating a power manager comprised in a system on chip (SoC), the method comprising:

• receiving a memory access level indicating a frequency of accesses to a memory from a memory controller;
• determining, by the power manager, whether the memory access level is equal to or higher than an access level threshold;
• and
• outputting a control signal for setting a supply power level of the memory,
• wherein, when the power manager determines that the memory access level is equal to or higher than the access level threshold, the outputting of the control signal comprises outputting a control signal for setting the supply power level of the memory to a new supply power level that is higher than a current supply power level, and
• wherein, when the power manager determines that the memory access level is not equal to or higher than the access level threshold, the method further comprises outputting a power decrease request signal regarding the memory to the memory controller.

A system on chip (SoC), comprising:

• a memory;
• a processor configured to execute instructions to control the memory;
• and
• a power manager configured to manage a supply power level of the memory,
• wherein, when executed by the processor, the instructions cause the system on chip to perform a process comprising:
• outputting, from the processor to the power manager, a memory access level indicating a frequency of accesses to the memory,
• adjusting, by the power manager, the supply power level of the memory according to the memory access level, and
• either delaying, by the processor, output of a response corresponding to an access of a master, or storing, by the processor, the access of the master in an access queue.

A system on chip (SoC), comprising:

• a memory;
• a processor configured to execute instructions to control the memory;
• and
• a power manager configured to manage a supply power level of the memory,
• wherein, when executed by the processor, the instructions cause the system on chip to perform a process comprising:
• outputting, from the processor to the power manager, a memory access level indicating a frequency of accesses to the memory,
• adjusting, by the power manager, the supply power level of the memory according to the memory access level, and
• outputting a fail signal in response to an access of a master.