Apparatus with inter-communicating processors

An apparatus comprising a first processor and a second processor, each having a first logic output pin, a second logic output pin, a first logic input pin and a second logic input pin, wherein:

• for each of the first and the second processor, the first logic output pin is connected to the second logic input pin of the respective other processor;
• for each of the first and the second processor, the second logic output pin is connected to the first logic input pin of the respective other processor;
• each of the first and the second processor is operable in a transmit mode for transmitting data to the respective other processor by controlling the second logic output pin to provide a logic data signal (DAT) indicating a sequence of data bits (D7-D0) and controlling the first logic output pin to provide a logic clock signal (CLK) with state transitions indicating when the logic data signal (DAT) indicates the values of the individual data bits (D7-D0) in the sequence;
• and
• each of the first and the second processor is operable in a receive mode for receiving data from the respective other processor by determining a sequence of data bits (D7-D0) from the logic data signal (DAT) received on the first logic input pin in response to state transitions of the logic clock signal (CLK) received on the second logic input pin;
• characterized in that each of the first and the second processor further is configured to:
• in dependence on being in the receive mode and able to receive data, control the second logic output pin to provide a logic clear-to-send signal (CTS) indicating the ability to receive data and control the first logic output pinto provide a logic data-acknowledge signal (ACK) with state transitions indicating successful reception of individual data bits (D7-D0);
• and
• in dependence on being in the transmit mode, delay transmission of the first data bit (D7-D0) in the sequence until determining that the logic clear-to-send signal (CTS) indicates the ability to receive data by the respective other processor and delay transmission of each subsequent data bit (D7-D0) in the sequence until determining a state transition of the logic data-acknowledge signal (ACK) that indicates successful reception of the respective previous data bit (D7-D0) by the respective other processor.