Robust secure testing of integrated circuits

An integrated circuit (IC) chip comprising:

• a plurality of blocks in which some blocks are configured to store secure data and other blocks are configured to store non-secure data, the plurality of data blocks comprises a plurality of scan chains, with each of the plurality of scan chains comprising a plurality of flip-flops and at least one of the plurality of scan chains including at least one flip-flop without a reset pin in the plurality flip-flops;
• and
• a scan security module configured to:
• in response to the IC chip receiving a test mode entry request, carry out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured to store the secure data or the non-secure data;
• shift a predetermined data pattern into the at last one flip-flop without the reset pin as part of the data-initialization operation;
• and
• disable an IC chip data output during the data-initialization operation.

A method comprising:

• providing an IC chip having a plurality of scan chains and at least one memory;
• receiving a test mode entry request in the IC chip having the plurality of scan chains and the at least one memory;
• and
• in response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of scan chains and the at least one memory, the data initialization operation including writing a first predetermined data pattern into the at least one memory to initialize the at least one memory, and reading a portion of the predetermined data pattern from the at least one memory into a pipeline register coupled to the at least one memory, thereby flushing the pipeline register.