Frequency synthesizer output cycle counter including ring encoder

A circuit, comprising:

• a ring encoder having an input coupled to receive a clock output from a frequency synthesizer, the ring encoder comprising a plurality of flip flops connected in series and at least one inverter coupled between a last flip flop of the plurality of flip flops and a first flip flop of the plurality of flip flops, the ring encoder configured to:
• generate a ring encoder output clock based on the clock output, wherein a frequency of the clock output is an integer multiple of a frequency of the ring encoder output clock;
• and
• generate an encoded output based on the clock output, wherein the encoded output indicates least significant bits (LSBs) of a clock cycle count of the clock output;
• a binary counter having an input coupled to receive the ring encoder, wherein the binary counter is configured to, based on the ring encoder output clock generate an output count indicating most significant bits (MSBs) of the clock cycle count;
• and
• a frequency estimator coupled to the ring encoder and to the binary counter, the frequency estimator configured to:
• sample, using a reference clock, the encoded output, to provide a sampled encoded output;
• and
• sample the output count, to provide a sampled output count.