Latch circuit and comparator circuit
AssigneeToshiba Memory Corporation
InventorMasayuki Usuda
Life of this patent
Estimating the term…
Abstract
A latch circuit includes first and second NAND circuits and first and second capacitive elements. The first NAND circuit has a first input node into which a first signal is input. The second NAND circuit has a first input node into which a second signal is input, a second input node which is connected to an output node of the first NAND circuit, and an output node which is connected to a second input node of the first NAND circuit. The first capacitive element has one end connected to the first input node of the first NAND circuit and has another end connected to the output node of the first NAND circuit. The second capacitive element has one end connected to the first input node of the second NAND circuit and has another end connected to the output node of the second NAND circuit.
Claims4
A latch circuit comprising:
- a first NAND circuit including an output node, a first input node and a second input node wherein a first signal is input into the first input node of the first NAND circuit;
- a second NAND circuit including an output node, a first input node and a second input node wherein a second signal is input into the first input node of the second NAND circuit, the second input node of the second NAND circuit is connected to the output node of the first NAND circuit, and the output node of the second NAND circuit is connected to the second input node of the first NAND circuit;
- a first capacitive element including one end connected to the first input node of the first NAND circuit and including another end connected to the output node of the first NAND circuit;
- and
- a second capacitive element including one end connected to the first input node of the second NAND circuit and including another end connected to the output node of the second NAND circuit.
A latch circuit comprising:
- a first NAND circuit including an output node, a first input node and a second input node wherein a first signal is input to the first input node of the first NAND circuit;
- a second NAND circuit including an output node, a first input node and a second input node wherein a second signal is input to the first input node of the second NAND circuit, the second input node of the second NAND circuit is connected to the output node of the first NAND circuit, and the output node of the second NAND circuit is connected to the second input node of the first NAND circuit;
- a third NAND circuit including a first input node and a second input node;
- and
- a fourth NAND circuit including a first input node and a second input node, wherein
- the first input node of the third NAND circuit is connected to the first input node of the first NAND circuit and the second input node of the third NAND circuit is connected to the output node of the first NAND circuit, and
- the first input node of the fourth NAND circuit is connected to the first input node of the second NAND circuit and the second input node of the fourth NAND circuit is connected to the output node of the second NAND circuit.
Dependencies are inferred from the claim text.