Power efficient high speed latch circuits and systems

A combiner latch circuit, comprising:

• an input circuit with a first input, a second input, a clock input, and an inverted clock input;
• an output circuit with a first differential output and a second differential output;
• wherein the input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of:
• a fourth state comprising the first differential output being at logic 1 and the second differential output being at logic 0;
• and
• a fifth state comprising the first differential output being at logic 0 and the second differential output being at logic 1;
• and
• wherein the input circuit is further configured to:
• select the fourth state when the first input is at logic 0 and the second input is at logic 1 and the clock input encounters a leading edge from logic 0 to logic 1 and the output circuit is in the fifth state;
• and
• select the fifth state when the first input is at logic 1 and the second input is at logic 0 and the clock input encounters a leading edge from logic 0 to logic 1 and the output circuit is in the fourth state.