Folded divider architecture
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorBeng-Heng Goh
Life of this patent
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Abstract
A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.
Claims46
A method, comprising:
- loading a clock divider counter with most significant bits of a divider value;
- decrementing the clock divider counter at a same edge of each pulse of a clock signal;
- comparing a value contained in the clock divider counter to a reference value and generating an end count signal as a function of the value contained in the clock divider counter matching the reference value, using logic circuitry;
- if the divider value is an integer, then:
- if the value contained in the clock divider counter is even, setting the reference value to 1;
- and
- if the value contained in the clock divider counter is odd, setting the reference value to 1, except for every other assertion of the end count signal where the reference value is instead set to 0;
- transitioning a toggle signal at a same edge of each pulse of the end count signal;
- reloading the clock divider counter with most significant bits of the divider value as a function of the end count signal;
- and
- generating a divided version of the clock signal as a function of the toggle signal.
A method, comprising:
- loading a clock divider counter with most significant bits of a divider value;
- decrementing the clock divider counter at a same edge of each pulse of a clock signal;
- comparing a value contained in the clock divider counter to a reference value and generating an end count signal as a function of the value contained in the clock divider counter matching the reference value, using logic circuitry;
- if the divider value is an integer, and if the value contained in the clock divider counter is even, setting the reference value to 1;
- transitioning a toggle signal at a same edge of each pulse of the end count signal;
- reloading the clock divider counter with most significant bits of the divider value as a function of the end count signal;
- and
- generating a divided version of the clock signal as a function of the toggle signal.
A method, comprising:
- loading a clock divider counter with most significant bits of a divider value;
- decrementing the clock divider counter at a same edge of each pulse of a clock signal;
- comparing a value contained in the clock divider counter to a reference value and generating an end count signal as a function of the value contained in the clock divider counter matching the reference value, using logic circuitry;
- if the divider value is an integer, and if the divider value is odd, setting the reference value to 1, except for every other assertion of the end count signal where the reference value is set to 0;
- transitioning a toggle signal at a same edge of each pulse of the end count signal;
- reloading the clock divider counter with most significant bits of the divider value as a function of the end count signal;
- and
- generating a divided version of the clock signal as a function of the toggle signal.
Dependencies are inferred from the claim text.