Semiconductor device structures
AssigneeVanguard International Semiconductor Corporation
InventorsTing-You Lin, Chi-Li Tu
Life of this patent
Estimating the term…
Abstract
Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also include an inner metal layer disposed on the semiconductor substrate and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion. The semiconductor device structures further include a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer.
Claims16
A semiconductor device structure, comprising:
- a semiconductor substrate;
- an inner metal layer disposed on the semiconductor substrate, wherein the inner metal layer includes a plurality of disconnected sections;
- a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers all the disconnected sections of the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion;
- a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer, and the first portion of the top metal layer is exposed by the hollowed pattern;
- and
- a polysilicon layer between the semiconductor substrate and the inner metal layer, wherein the polysilicon layer is not covered by the second portion of the top metal layer and the passivation layer.
A semiconductor device structure, comprising:
- a semiconductor substrate;
- an inner metal layer disposed on the semiconductor substrate, wherein the inner metal layer includes a plurality of disconnected sections that are electrically connected to a polysilicon layer disposed between the inner metal layer and the semiconductor substrate;
- a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion that surrounds the first portion, and wherein the first portion covers all the disconnected sections of the inner metal layer;
- and
- a passivation layer disposed on the top metal layer, wherein the passivation layer comprises a first passivation portion and a second passivation portion separated from the first passivation portion, the second passivation portion surrounds the first passivation portion, and the top metal layer is exposed by a gap between the first passivation portion and second passivation portion, and wherein the polysilicon layer is not covered by the passivation layer, and a portion of the polysilicon layer is a thin film resistor.
Dependencies are inferred from the claim text.