System and method for providing power savings in an access point via ethernet rate and interface shifting

A system for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the system comprising:

• a processor;
• and
• a computer-readable storage device storing instructions which, when executed by the processor, cause the processor to perform operations comprising:
• determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
• when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
• selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size;
• and
• switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
• wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.

A non-transitory computer-readable storage device storing instructions for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the instructions when executed by a processor cause the processor to perform operations comprising:

• determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
• when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
• selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size;
• and
• switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
• wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.