US 10,375,334 B2Granted

Image sensor and electronic apparatus including multiple substrates

AssigneeSony Corporation

InventorsTsutomu Nakajima, Atsushi Muto

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Abstract

The present technology relates to an image sensor and an electronic apparatus which can make the image sensor a smaller without degrading performance of the image sensor. The image sensor includes a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner, a row circuit configured to control row scanning of the pixel array unit, and a column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is disposed on a first-layer substrate, and the row circuit and the column processing unit are disposed on different substrates which are underlying layers of the first-layer substrate and which are laminated on the first-layer substrate. The present technology is applicable to the image sensor.

Claims13

Dependent claims

An image sensor comprising:

a first substrate including a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner, the pixel array unit having a first edge and a second edge that is longer than the first edge in a plan view, the first edge extending in a first direction, the second edge extending in a second direction that is perpendicular to the first direction;
a second substrate including a memory;
and
a third substrate including a column processing unit, the column processing unit including a comparator and a counter, the column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal,
wherein the first substrate, the second substrate, and the third substrate are laminated,
wherein the comparator includes a first portion and a second portion,
wherein the counter includes a first portion and a second portion,
wherein, in the plan view, the first portions and the second portions are spaced apart from each other in the first direction, and
wherein the first portions and the second portions have equal lengths in the second direction and are aligned with one another in the first direction.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/971,460Filed 4 May 2018 · continuation
Priority: JP 2014-08336415 Apr 2014
Published: US 2018/0255260 A16 Sep 2018
Granted: 6 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H04N 25/76
SSIS architectures; Circuits associated therewith: addressed sensors, e.g. MOS or CMOS sensors
H04N 25/772
Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components: comprising A/D, V/T, V/F, I/T or I/F…
H04N 25/779
Addressed sensors, e.g. MOS or CMOS sensors: circuitry for scanning or addressing the pixel array
H04N 25/7795
Addressed sensors, e.g. MOS or CMOS sensors: circuitry for generating timing or clock signals

Family

PCT/JP2015/060551Parent of this continuation · filed 3 Apr 2015
US 2018/0255260 A1Pre-grant publication · published 6 Sep 2018
Application15/127,510Parent of this continuation
US 10,015,427 B2Parent of this continuation
US 2017/0155865 A1Published application
US 10,375,334 B2This patent

From the US filing history. Foreign family members aren’t listed.

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