Input signal decoding circuit for receiver side in mobile industry processor interface C-Phy

An input signal decoding circuit for a receiver (RX) side in a mobile industry processor interface (MIPI) C-Phy, the input signal decoding circuit comprising:

• an equalizer circuit module connected to a transmitter (TX) side of an MIPI via three signal wires and configured to sample signals of the signal wires to acquire a first data signal, a second data signal and a third data signal;
• a clock recovery circuit module configured to acquire an operating clock signal from the first data signal, the second data signal and the third data signal;
• a decoding circuit module configured to output a Flip signal, a Rotation signal and a Polarity signal based on the first data signal, the second data signal, the third data signal and the operating clock signal;
• and
• a serial-to-parallel conversion module configured to output 21-bit parallel data based on the Flip signal, the Rotation signal and the Polarity signal.