Equalization for transmitter input buffer array
AssigneeInphi Corporation
InventorsKarim Abdelhalim, Michael Le, Haidang Lin
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Abstract
The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.
Claims20
An input buffer device comprising:
- a first input terminal;
- a first input slice including a first plurality of inverters that comprises n inverters configured in series, n indicating a first quantity of inverters and being two or greater, the first plurality of inverters including a first inverter and a first group of m inverters, m indicating a second quantity of inverters, the first inverter being coupled to the first input terminal;
- and
- a first equalization element characterized by a predetermined resistance value, the predetermined resistance value being based on a delay associated with the first group of m inverters, the first equalization element being configured in series relative to the first group of m inverters.
A circuit device comprising:
- a DAC device configured to convert n bits of input data, n indicating a number of bits;
- a first input buffer module comprising a first plurality of inverters and a first equalization element, the first input buffer module being configured to provide a first input signal to the DAC device, the first plurality of inverters includes a first a segment of m inverters, m indicating a quantity of inverters, the first segment of m inverters being associated with a first delay value, the first equalization element being characterized by a first predetermined resistance value, the first predetermined resistance value being determined based on the first delay value;
- and
- a pre-distortion array coupled to the first input buffer module.
A data input buffer device comprising:
- a first input terminal;
- a first plurality of inverters comprising n inverters configured in series, n indicating a first quantity of inverters and being two or greater, the first plurality of inverters including a first inverter and a first group of m inverters, m indicating a second quantity of inverters, the first inverter being coupled to the first input terminal;
- a first output terminal coupled to the first plurality of inverters;
- a second input terminal;
- a second plurality of inverters comprising n inverters configured in series, the second plurality of inverters including a second inverter and a second group of m inverters, the second inverter being coupled to the second input terminal;
- a first equalization element being characterized by a first predetermined resistance value, the first predetermined resistance value being based on a delay associated with the second group of m inverters, the first equalization element being configured in series relative to the second group of m inverters;
- a switch coupled to the first equalization element;
- and
- a second output terminal coupled to the second plurality of inverters.
Dependencies are inferred from the claim text.