Clock phase adjustment using clock and data recovery scheme

An apparatus comprising:

• an input to receive an input signal;
• an input clock generator to generate an input clock signal;
• first and second clock generators to generate a first clock signal and a second clock signal, respectively, based on the input clock signal, the first and second clock signals having different phases;
• sampler circuitry to sample the input signal based on timing of the first and second clock signals and provide data information and error information associated with the sampling of the input signal;
• a clock and data recovery unit to generate first control information based on the data information and the error information and provide the first control information to the input clock generator;
• and
• a phase error detection unit to generate second control information based on the data information and the error information and to provide the second control information to the first and second clock generators, wherein the sampler circuitry includes:
• a first circuit path to sample the input signal based on timing of the first clock signal and provide a first portion of the data information and a first portion of error information;
• and
• a second circuit path to sample the input signal based on timing of the second clock and provide a second portion of the data information and a second portion of the error information.