Increasing communication safety by preventing false packet acceptance in high-speed links

An apparatus comprising:

• Physical Layer (PHY) circuitry, including,
• a transmitter port including transmitter circuitry for four transmit lanes;
• and
• a receiver port including receiver circuitry for four receive lanes;
• a Physical Coding Sublayer (PCS) module including a bit error ratio (BER) monitor;
• a Reed-Solomon Forward Error Correction (RS-FEC) module coupled to the PCS module and configured to,
• detect correctable symbol errors;
• correct the correctable symbol errors;
• pass through uncorrectable symbol errors without marking;
• and
• determine if a correctable symbol error ratio (SER) exceeds a correctable SER threshold,
• wherein the apparatus is further configured to be implemented in a high-speed link and disconnect or temporarily pause the high-speed link when it is determined the correctable SER exceeds the correctable SER threshold to prevent false packet acceptance, and
• wherein in response to detection of a correctable SER exceeding the correctable SER threshold the RS-FEC module is configured to forward blocks with corrupted sync headers to the PCS module, and the BER monitor is configured to detect the corrupted sync headers and generate a hi_ber condition.

An apparatus comprising:

• Physical Layer (PHY) circuitry, including,
• a transmitter port including transmitter circuitry for four transmit lanes;
• and
• a receiver port including receiver circuitry for four receive lanes;
• a Physical Coding Sublayer (PCS) module;
• a Reed-Solomon Forward Error Correction (RS-FEC) module coupled to the PCS module;
• a Media Access Control (MAC) module;
• a Reconciliation Sublayer (RS) module;
• and
• a Peripheral Component Interconnect Express (PCIe) interface;
• wherein the RS-FEC module is configured to,
• pass through uncorrectable symbol errors without marking;
• detect correctable symbol errors;
• correct the correctable symbol errors;
• and
• determine if a correctable symbol error ratio (SER) exceeds a correctable SER threshold,
• wherein the apparatus is further configured to be implemented in a high-speed link and in response to determining a correctable SER exceeds the correctable SER threshold continuously corrupt block sync headers to generate a hi_ber condition for a predetermined period and disconnect or temporarily pause the high-speed link after the predetermined period to prevent false packet acceptance.

A system comprising:

• a chassis;
• an inter-plane, mounted within the chassis, having first and second inter-plane connectors and wiring coupled therebetween configured to facilitate a multi-lane 100 Gigabits per second (Gb/s) Ethernet link;
• a first board having a first network interface controller (NIC) including 100 Gb/s Ethernet transmitter and receiver ports operatively coupled to a first board connector that is coupled to the first inter-plane connector;
• a second board having a second NIC including 100 Gb/s Ethernet transmitter and receiver ports operatively coupled to a second board connector that is coupled to the second inter-plane connector,
• wherein the 100 Gb/s Ethernet transmitter for each of the first and second NICs is configured to transmit data over four transmit lanes, and the first NIC is configured, when the system is operating,
• receive data from the second NIC via the 100 Gb/s Ethernet link;
• pass through uncorrectable symbol errors without marking;
• detect correctable symbol errors and correct the correctable symbol errors;
• determine if a correctable symbol error ratio (SER) exceeds a correctable SER threshold;
• and,
• in response thereto,
• continuously corrupt block sync headers to generate a hi_ber condition for a predetermined period and disconnect the 100 Gb/s Ethernet link after the predetermined period to prevent false packet acceptance.