Multi-tier time-synchronization architecture
AssigneeAltera Corporation
InventorsSita Rama Chandrasekhar Mallela, Seng Kuan Yeow
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Abstract
Devices and methods to design and use network interfaces compliant with time-synchronization protocols via a multi-tier architecture are provided. This architecture allows for independent development between circuitry related to the time-synchronization protocols and circuitry responsible for channel access, reducing redundancies in the design process.
Claims20
An electronic device that connects to a common-channel network and complies with a time-synchronization protocol, the electronic device comprising:
- a clock that generates a plurality of timestamps;
- first MAC circuitry that:
- receives an RX MAC packet from the common-channel network using a Media Access Control protocol;
- and
- sends a TX MAC packet to the common-channel network using the Media Access Control protocol;
- first time-synchronization circuitry separate from the first MAC circuitry, wherein the first time-synchronization circuitry parses the RX MAC packet in accordance with the time-synchronization protocol based at least in part on one of the plurality of timestamps from the clock;
- second time-synchronization circuitry separate from the first MAC circuitry, wherein the second time-synchronization circuitry parses the TX MAC packet and generates time-synchronization data to be inserted in the TX MAC packet in accordance with the time-synchronization protocol based at least in part on one of the plurality of timestamps from the clock and a time-synchronization protocol command of the TX MAC packet;
- and
- extractor/inserter circuitry coupled between the first MAC circuitry and the second time-synchronization circuitry, wherein the extractor/inserter circuitry:
- extracts a time-synchronization protocol command directed to the second time-synchronization circuitry from the TX MAC packet before the TX MAC packet is sent by the first MAC circuitry;
- provides the time-synchronization protocol command to the second time-synchronization circuitry;
- receives the time-synchronization data from the second time-synchronization circuitry;
- and
- edits the TX MAC packet in accordance with the time-synchronization protocol to insert the time-synchronization data into the TX MAC before the TX MAC packet is sent by the first MAC circuitry.
Three-tier network circuitry compliant with a time-synchronization protocol, the three-tier network circuitry comprising:
- a first tier that includes MAC circuitry that sends a TX MAC packet;
- a second tier that includes:
- extractor circuitry that parses the TX MAC packet and extracts a time-synchronization command;
- and
- inserter circuitry that edits the TX MAC packet based at least in part on time-synchronization data, in accordance with the time-synchronization protocol;
- and
- a third tier that includes first time-synchronization circuitry that generates the time-synchronization data based at least in part on the time-synchronization command.
A method comprising:
- generating media access control (MAC) outgoing packet using data utilization circuitry that includes an IEEE 1588 command compliant with the IEEE 1588 standard;
- providing the MAC outgoing packet from the data utilization circuitry to first modular circuitry that includes MAC circuitry compliant with the IEEE 802.3 standard and second modular circuitry that includes extractor circuitry and inserter circuitry, wherein the first modular circuitry is distinct from the second modular circuitry;
- using the extractor circuitry of the second modular circuitry to extract the IEEE 1588 command from the MAC outgoing packet;
- providing the IEEE 1588 command from the second modular circuitry to third modular circuitry that includes IEEE 1588 calculation circuitry compliant with the IEEE 1588 standard, wherein the third modular circuitry is distinct from the first modular circuitry and the second modular circuitry;
- using the third modular circuitry to generate time-synchronization data based at least on the IEEE 1588 command;
- providing the time-synchronization data from the third modular circuitry to the second modular circuitry;
- providing the MAC outgoing packet from the first modular circuitry to the inserter circuitry of the second modular circuitry;
- and
- using the inserter circuitry of the second modular circuitry to edit the MAC outgoing packet based at least in part on the time-synchronization data;
- providing the edited MAC outgoing packet from the inserter circuitry of the second modular circuitry to the first modular circuitry;
- and
- sending the edited MAC outgoing packet using the first modular circuitry.
Dependencies are inferred from the claim text.