Circuit structure and method for high-speed forward error correction

A transmitter for a multi-lane data link, the transmitter comprising:

• a plurality of physical media attachment circuits for serializing data for a plurality of serial lanes of the multi-lane data link, each physical media attachment circuit receiving the data at a first bus width;
• a plurality of gearbox circuits, each gearbox circuit outputting the data at the first bus width and receiving the data at a second bus width, wherein the first bus width is different from the second bus width;
• and
• a forward error correction (FEC) encoder for encoding and outputting the data at a third bus width, wherein the third bus width in bits is a product of the second bus width in bits and a number of the serial lanes of the multi-lane data link, and wherein the data is encoded with an FEC code having a block length,
• wherein the third bus width in bits is an exact multiple of a number of bits per symbol in the data, and
• wherein the third bus width in bits is an exact multiple of a number of serial lanes of the multi-lane interface.

A forward error correction (FEC) circuit for a multi-lane interface, the FEC circuit comprising:

• an output bus having a bus width;
• an FEC encoder for, encoding data received on the output bus, wherein the data is encoded with an FEC code having a block length;
• and
• an input bus for receiving the encoded data from the FEC encoder,
• wherein the bus width in bits is an exact multiple of a number of bits per symbol in the data, and
• wherein the block length in bits is an exact multiple of the bus width.

A forward error correction (FEC) circuit for a multi-lane interface, the FEC circuit comprising:

• an output bus having a bus width;
• an FEC encoder for encoding data for output on the output bus, wherein the data is encoded with an FEC code having a block length;
• and
• an input bus for receiving the data for the FEC encoder,
• wherein the bus width in bits is an exact multiple of a number of bits per symbol in the data, and
• wherein the bus width in bits is an exact multiple of a number of serial lanes of the multi-lane interface.