Low-density parity check decoder, a storage device including the same, and a method

A storage device comprising:

• a nonvolatile memory (NVM) device that stores a codeword including information and a parity corresponding to the information;
• and
• a memory controller including a low-density parity check (LDPC) decoder that reads the codeword from the NVM device and corrects an error of the codeword, wherein:
• the LDPC decoder comprises:
• a variable node processor that receives channel information and check node information corresponding to the codeword and updates variable node information;
• and
• a check node processor that receives the variable node information and updates the check node information, and
• the check node processor:
• comprises K>2 memory elements that provide a K-cycle cyclic permutation and L of the memory elements, where 1<L<K, provide an L-cycle cyclic permutation;
• and
• executes a first LDPC on data stored by the memory elements using the K-cycle cyclic permutation and the L-cycle cyclic permutation, wherein
• a number of cycles required to execute the first LDPC is smaller than a number of cycles required to execute a second LDPC on the data using only the K-cycle cyclic permutation.

A method for performing a read operation in a storage device performing hard decision memory sensing in the storage device, the method comprising:

• transmitting read data from a non-volatile memory (NVM) device of the storage device to an error correction circuit of a memory controller of the storage device;
• in a low-density parity check (LDPC) decoder of the error correction circuit, using LDPC decoding to make a hard decision on the read data;
• in the LDPC decoder, determining whether the hard decision was successfully made;
• in response to determining that the hard decision was not successfully made, performing soft decision memory sensing on the read data;
• transmitting the read data from the NVM device to the error correction circuit of the memory controller;
• in the LDPC decoder of the error correction circuit, performing a soft decision using LDPC decoding on the read data;
• and
• in the LDPC decoder, determining whether the soft decision was successfully made, wherein the LDPC decoder:
• comprises K>2 memory elements that provide a K-cycle cyclic permutation and L of the memory elements, where 1<L<K, provide an L-cycle cyclic permutation,
• executes a first LDPC on data stored by the memory elements using the K-cycle cyclic permutation and the L-cycle cyclic permutation, and
• performs the first LDPC decoding to make the hard decisions and the soft decisions, wherein
• a number of cycles required to execute the first LDPC is smaller than a number of cycles required to execute a second LDPC on the data using only the K-cycle cyclic permutation.