US 10,374,625 B2Granted

Capacitor layout of digital-to-analog conversion integrated circuit

AssigneeRealtek Semiconductor Corp.

InventorsShih-Hsiung Huang, Sheng-Hsiung Lin

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Abstract

The present invention discloses a capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), comprising a first capacitor group, a second capacitor group and a third capacitor group. The first capacitor group, located within an interior layout area of the capacitor layout, determines a most significant bit (MSB) of the DAC IC and includes a plurality of capacitor units coupled between a first upper circuit and a first lower circuit. The second capacitor group, located within the interior layout area, determines a non-MSB bit of the DAC IC and includes at least one capacitor unit(s) coupled between a second upper circuit and a second lower circuit. The third capacitor group includes a plurality of capacitor units coupled between a third upper circuit and a third lower circuit which are not short-circuited; the capacitor units of the third capacitor group are disposed around the interior layout area.

Claims20

Dependent claims

A capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), the capacitor layout of the DAC IC comprising:

a plurality of capacitor groups including:
a first capacitor group being dominant in determining a first bit of the DAC IC, the first capacitor group including M first capacitance units that are coupled between a first upper circuit and a first lower circuit and located within an interior layout area of the capacitor layout of the DAC IC, in which the M is an integer greater than one;
a second capacitor group for determining a second bit of the DAC IC, the second capacitor group including N second capacitance unit(s) that are coupled between a second upper circuit and a second lower circuit and located within the interior layout area, in which the N is a positive integer;
and
a third capacitor group including X third capacitance units that are coupled between a third upper circuit and a third lower circuit, in which the third upper circuit and the third lower circuit are not short-circuited, the X third capacitance units are located outside the interior layout area and disposed next a plurality of sides of the interior layout area, and the X is an integer greater than one,
wherein the first bit is a most significant bit of the DAC IC, a number of capacitance units of the third capacitor group is not less than a number of capacitance units of the first capacitor group, and a capacitance of the third capacitor group is less than a capacitance of the first capacitor group.

3 more elements

A capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), the capacitor layout of the DAC IC comprising:

a plurality of capacitor groups including:
a first capacitor group being dominant in determining a first bit of the DAC IC, in which the first capacitor group is coupled between a first upper circuit and a first lower circuit and located within an interior layout area of the capacitor layout of the DAC IC;
a second capacitor group for determining a second bit of the DAC IC, in which the second capacitor group is coupled between a second upper circuit and a second lower circuit and located within the interior layout area;
and
a third capacitor group coupled between a third upper circuit and a third lower circuit, in which the third upper circuit and the third lower circuit are not short-circuited, and the third capacitor group is located outside the interior layout area and disposed next a plurality of sides of the interior layout area,
wherein the first lower circuit and the second lower circuit include a low voltage supply terminal, the third lower circuit includes a voltage terminal, and the low voltage supply terminal is different from the voltage terminal.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/855,149Filed 27 Dec 2017
Priority: TW 106116780 A19 May 2017
Published: US 2018/0337688 A122 Nov 2018
Granted: 6 Aug 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03M 1/802
Using weighted impedances: using capacitors, e.g. neuron-mos transistors, charge coupled devices
H03M 1/68
Digital/analogue converters: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and…
H03M 1/468
Using switched capacitors: in which the input S/H circuit is merged with the feedback DAC array
H03M
Coding

Family

US 2018/0337688 A1Pre-grant publication · published 22 Nov 2018
US 10,374,625 B2This patent

From the US filing history. Foreign family members aren’t listed.

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