Frequency locked loop with multi-bit sampler

Abstract

The present disclosure relates to a frequency locked loop including a frequency detection unit, a local oscillator, and a multi-bit sampler. The frequency detection unit is configured to receive a reference frequency parameter and a sub-sampled frequency parameter, and configured to generate a digital frequency difference, which is a difference indication between the reference frequency parameter and the sub-sampled frequency parameter. The local oscillator is configured to generate an output signal based on the digital frequency difference. The multi-bit sampler is configured to update the sub-sampled frequency parameter by sub-sampling the output signal with N (N>=2) sampling-clocks. The N sampling-clocks have a same sampling frequency and are sequentially offset by an equal time delay between adjacent sampling-clocks. The updated sub-sampled frequency parameter monotonically maps an output frequency of the output signal.

Dependencies are inferred from the claim text.