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US 10,374,616 B2Granted
Phase frequency detector
AssigneeIntel Corporation
InventorsWenyan Vivian Jia, Shenggao Li, Fulvio Spagna
Life of this patent
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Abstract
Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
Claims19
An apparatus comprising:
- a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference by expressing higher ordered bits of a digital code that specifies a phase difference;
- and
- a second PFD to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference by expressing a lower ordered bit adjustment to the digital code.
A phase frequency detector (PFD) comprising:
- a time-to-digital converter (TDC) to determine a coarse phase difference between a reference clock signal and a feedback clock signal, the TDC to generate a first output indicating the coarse phase difference by expressing higher ordered bits of a digital code that specifies a phase difference;
- a bang-bang PFD (BBPFD) to determine a fine phase difference between the reference clock signal and the feedback clock signal, the BBPFD to generate a second output indicating the fine phase difference by expressing a lower ordered bit adjustment to the digital code.
A system comprising:
- a memory;
- a processor, coupled to the memory, the processor including:
- a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference by expressing higher ordered bits of a digital code that specifies a phase difference;
- and
- a second PFD to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference by expressing a lower ordered bit adjustment to the digital code;
- and
- a wireless interface for communicatively coupling the processor to another device.
4 more elements
Dependencies are inferred from the claim text.